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[AKD4686-B] a k4686 evaluation board rev.0 AKD4686-B feature AKD4686-B is an evaluation board for ak4686, a singl e chip 24bit codec that has one stereo adc and two stereo dac. this board has in terfaces with akm?s evaluation boards for a/d converter and d/a converter and makes easy to evaluate ak4686. also this board has the digita l audio interface and then achieves the interface with digita l audio systems via rca connector. ? ordering guide AKD4686-B --- evaluation board for ak4686 (cable for connecting with printer port of ibm-at compatible pc and control software are packed with this. this control software does not operate on windows nt.) function ? on-board clock generators (ak4118 x 2) ? compatible with 2 types of digital audio interface - rca (s/pdif) input/output - 10pin headers for interfacing with external data source (x2) ? rca connectors for clock input with external clock source ? 10pin header for register control gnd ak4686 +5v regulator lout1/rout1 lout2/rout2 +3.3v lin / rin control data 10pin header rca out rca in 10pin header port 1 ex1 ak4118 (dit/dir) ex2 10pin header port 2 ak4118 (dir) rca in figure 1. AKD4686-B block diagram (* circuit diagram and pcb layout are attached at the end of this manual.) < km103800> 2010/08 - 1 -
[AKD4686-B] evaluation board manual ? operating sequence 1. set up power supply lines. name of jack color of jack voltage used for comment and attention default +5v red +4.5 +5.5v regulator t2, t5 should be always connected +5v avdd1 orange +3.0 +3.6v avdd1 of ak4686 should be open when jp40 (avdd1_sel) is set to reg side. should be connected when jp40 (avdd1_sel) is set to avdd1 side. open avdd2 orange +3.0 +3.6v avdd2 of ak4686 should be open when jp41 (avdd2_sel) is set to reg side. should be connected when jp41 (avdd2_sel) is set to avdd2 side. open dvdd orange +3.0 +3.6v dvdd of ak4686 should be open when jp42 (dvdd_sel) is set to reg side. should be connected when jp42 (dvdd_sel) is set to dvdd side. open cvdd orange +3.0 +3.6v cvdd of ak4686 should be connected when default. should be open in case of using regulator t2 when r85 is short and l7 is open. +3.3v d3.3v orange +3.0 +3.6v power supply of logic should be open when jp45 (d3.3v_sel) is set to reg side. should be connected when jp45 (d3.3v_sel) is set to d3.3v side. open vss1 black 0v analog ground should be always connected 0v vss2 black 0v analog ground should be always connected 0v vss3 black 0v analog ground should be always connected 0v vss4 black 0v analog ground should be always connected 0v dgnd black 0v digital ground should be always connected 0v table 1. power supply lines each supply line should be distributed from the power supply unit. 2. set up evaluation mode and jumper pins. (refer to the following item.) 3. connect cables. (refer to the following item.) 4. power on. the ak4686 (u1) should be reset once bringing sw1 (pdn) ?l? upon power-up. keep ?h? during normal operaion. 5. set up control software registers. (refer to the following item.) < km103800> 2010/08 - 2 -
[AKD4686-B] ? evaluation modes (1) dac with external dir (synchronous mode) 1. connection of connector for digital (s/pdif) input, rca connectors j12 (port1 rx0) and j15 (port2 rx0) are available. for analog output, rca connectors j5 (lout1)/jp6 (rout1), j7 (lout2)/j8 (rout2) are available. 2. setting of jumper pin setting of interface signal of port1: ak4118 (u4) is as follows. jp19 jp20 jp21 jp22 jp23 jp50 jumper xti1 mcko_sel1 mclk1_sel bick1_sel lrck1_sel sdti1 setting open mcko1 short short short short (default) table 2. setting of interface signa l of port1: ak4118 (u4) (1/3) setting of interface signal of port2: ak4118 (u7) is as follows. jp26 jp27 jp28 jp29 jp30 jp31 jumper xti2 mcko_sel2 mclk2_sel bick2_sel lrck2_sel sdti2_sel setting open don?t care mcdir1 bidir1 lrdir1 sddir1 table 3. setting of interface signa l of port2: ak4118 (u7) (1/3) 3. setting of toggle switch switch sw2 sw5 sw6 sw7 setting h l h h table 4. setting of interface signal of port1, port2: ak4118 (u4,u7) (2/3) 4. setting of dip switch sw3 switch dif0 dif1 dif2 cm0 ocks0 ocks1 setting h l h l l h table 5. setting of interface signa l of port1: ak4118 (u4) (3/3) sw4 switch dif0 dif1 dif2 cm0 ocks0 ocks1 setting don?t care don?t care don?t care don?t care don?t care don?t care table 6. setting of interface signa l of port2: ak4118 (u7) (3/3) < km103800> 2010/08 - 3 -
[AKD4686-B] (2) dac with external dir (asynchronous mode) 1. connection of connector for digital (s/pdif) input, rca connectors j12 (port1 rx0) and j15 (port2 rx0) are available. for analog output, rca connectors j5 (lout1)/jp6 (rout1), j7 (lout2)/j8 (rout2) are available. 2. setting of jumper pin setting of interface signal of port1: ak4118 (u4) is as follows. jp19 jp20 jp21 jp22 jp23 jp50 jumper xti1 mcko_sel1 mclk1_sel bick1_sel lrck1_sel sdti1 setting open mcko1 short short short short (default) table 7. setting of interface signa l of port1: ak4118 (u4) (1/3) setting of interface signal of port2: ak4118 (u7) is as follows. jp26 jp27 jp28 jp29 jp30 jp31 jumper xti2 mcko_sel2 mclk2_sel bick2_sel lrck2_sel sdti2_sel setting open mcko1 mcdir2 bidi r2 lrdir2 sddir2 (default) table 8. setting of interface signa l of port2: ak4118 (u7) (1/3) 3. setting of toggle switch switch sw2 sw5 sw6 sw7 setting h h h h table 9. setting of interface signal of port1, port2: ak4118 (u4, u7) (2/3) 4. setting of dip switch sw3 switch dif0 dif1 dif2 cm0 ocks0 ocks1 setting h l h l l h (default) table 10. setting of interface signa l of port1: ak4118 (u4) (3/3) sw4 switch dif0 dif1 dif2 cm0 ocks0 ocks1 setting h l h l l h (default) table 11. setting of interface signa l of port2: ak4118 (u7) (3/3) < km103800> 2010/08 - 4 -
[AKD4686-B] (3) adc with external dit 1. connection of connector for analog input, rca connector jl1(lin1), jl2(lin2), jl3(lin3), jl4(lin4), jl5(lin5), jl6(lin6) and jr1(rin1), jr2(rin2), jr3(rin3), jr4(rin4), jr5(rin5), jr6(rin6) are available. for digital (s/pdif) output, rca connector j13 (port1 tx1) is available. 2. setting of jumper pin setting of interface signal of port1: ak4118 (u4) is as follows. x1 (24.576mhz) is used as clock (512fs) . jp19 jp20 jp21 jp22 jp23 jp24 jumper xti1 mcko1_sel mclk1_sel bick1_sel lrck1_sel sdto1_sel setting open mcko1 short short short short (default) table 12. setting of interface signa l of port1: ak4118 (u4) (1/3) 3. setting of toggle switch switch sw2 sw5 setting h l table 13. setting of reset of port1 ak4118 (u4) (2/3) 4. setting of dip switch sw3 switch dif0 dif1 dif2 cm0 ocks0 ocks1 ms1 setting h l h h l h l table 14. setting of interface signa l of port1: ak4118 (u4) (3/3) < km103800> 2010/08 - 5 -
[AKD4686-B] ? register control AKD4686-B can be controlled via the printer port (parallel port) of ibm-at compatible pc. connect port3 (up-i/f) to pc by 10-line flat cable packed with this. take car e of the direction of connector. sda sda ( ack ) scl AKD4686-B 10-pin header 10-pin connector 10-wire fl at cable connect pc red 9 1 2 port3 up-i/f 10 figure 2. port1 pin layout ? set-up dip switch (sw3, 4) no. name content default sw3-1 dif0 on sw3-2 dif1 off setting of ak4118 audio interface format table 16 .) (refer sw3-3 dif2 on selection of ak4118 clock mode (clock source) sw3-4 cm0 off table 17 .) (refer sw3-6 ocks0 off sw3-7 ocks1 selection of ak4118 master clock output frequency table 18 .) (refer on port1 master mode/slave mode switch sw3-8 ms1 off (refer to the ak4686?s datasheet) sw4-1 dif0 on sw4-2 dif1 off setting of ak4118 audio interface format (refer table 16 .) sw4-3 dif2 on selection of ak4118 clock mode (clock source) sw4-4 cm0 off table 17 .) (refer sw4-6 ocks0 off sw4-7 ocks1 selection of ak4118 master clock output frequency (refer table 18 .) on table 15. set up modes of ak4118 (u4, u7) and ak4686 (u1) lrck bick mode dif2 dif1 dif0 daux sdto i/o i/o 0 0 0 0 24bit, left justified 16bit, right justified h/l o 64fs o 1 0 0 1 24bit, left justified 18bit, right justified h/l o 64fs o 2 0 1 0 24bit, left justified 20bit, right justified h/l o 64fs o 3 0 1 1 24bit, left justified 24bit, right justified h/l o 64fs o 4 1 0 0 24bit, left justified 24bit, left justified h/l o 64fs o 5 1 0 1 24bit, i 2 s 24bit, i 2 s l/h o 64fs o 6 1 1 0 24bit, left justified 24bit, left justified h/l i 64-128fs i 7 1 1 1 24bit, i 2 s 24bit, i 2 s l/h i 64-128fs i table 16. ak4118 audio interface format mode cm0 pll x'tal clock source sdto 0 0 on on pll rx 1 1 off on x'tal daux table 17. ak4118 clock mode (clock source) < km103800> 2010/08 - 6 -
[AKD4686-B] no. ocks1 ocks0 mcko1 mcko2 x?tal fs (max) 0 0 0 256fs 256fs 256fs 96 khz 1 0 1 256fs 128fs 256fs 96 khz 2 1 0 512fs 256fs 512fs 48 khz 3 1 1 128fs 64fs 128fs 192 khz table 18. ak4118 master clock output frequency ? toggle switch [sw1] pdn: a switch for power down reset of ak4686 (u1). keep ?h? during operation of ak4686 (u1). power down reset of ak4686 will be done by setting sw1 to ?l? once, after power on. [sw2] ak4118 (u4)-pdn: a switch for power down reset of ak4118 (u4). keep ?h? during operation of ak4118 (u4). power down reset of ak4118 (u4) will be done by setting sw2 to ?l? once, after power on. [sw5] ak4118 (u7)-pdn: a switch for power down reset of ak4118 (u7). keep ?h? during operation of ak4118 (u7). power down reset of ak4118 (u7) will be done by setting sw5 to ?l? once, after power on. [sw6] mt1n: a switch for lout1/rout1 mute control. keep sw6 ?h? during normal operation of ak4686 (u1)?s dac1. analog output will be muted by setting sw6 to ?l?. refer to page 20 of ak4686?s datasheet for analog soft mute function of ak4686. [sw7] mt2n: a switch for lout2/rout2 mute control. keep sw7 ?h? during normal operation of ak4686 (u1)?s dac2. analog output will be muted by setting sw7 to ?l?. refer to page 20 of ak4686?s datasheet for analog soft mute function of ak4686. ? led indication [led1] erf: an error detection for ak4118(u4). it turns on when output of ak4118 (u4): int0 is ?h?. [led2] erf: an error detection for ak4118(u7). it turns on when output of ak4118 (u7): int0 is ?h?. < km103800> 2010/08 - 7 -
[AKD4686-B] ? analog input circuit lin3 jl3 mr-552ls 2 3 1 + c7 (short) vss1 rin3 jr3 mr-552ls 2 3 1 + c8 (short) vss1 rin5 jr5 mr-552ls 2 3 1 + c15 (short) vss1 lin5 jl5 mr-552ls 2 3 1 + c14 (short) vss1 rin4 jr4 mr-552ls 2 3 1 vss1 + c11 (short) lin4 jl4 mr-552ls 2 3 1 vss1 + c10 (short) lin1 lin1 lin2 lin3 lin4 lin5 lin6 lin2 jl2 mr-552ls 2 3 1 + c1 (short) vss1 rin2 jr2 mr-552ls 2 3 1 + c3 (short) vss1 rin1 rin2 rin3 rin4 rin5 rin6 rin6 jr6 mr-552ls 2 3 1 + c29 (short) vss1 lin6 jl6 mr-552ls 2 3 1 + c28 (short) vss1 rin1 jr1 mr-552ls 2 3 1 + c27 (short) vss1 jl1 mr-552ls 2 3 + c26 (short) 1 vss1 figure 3. analog input circuit for analog input, rca connector: jl1(lin1), jl2(lin2), jl3(lin3), jl4(lin4), jl5(lin5), jl6(lin6) and jr1(rin1), jr2(rin2), jr3(rin3), jr4(rin4), jr5(rin5), jr6(rin6) are available to use. analog inputs are single-e nded and input range of each channel is 2.2vrms (typ) when avdd1=3.3vrms. < km103800> 2010/08 - 8 -
[AKD4686-B] ? analog output circuit vss2 vss2 r45 (open) r43 (short) + c30 (short) lout1 lout1 vss2 + c32 (open) j5 mr-552ls 2 3 1 vss2 vss2 vss2 r50 (open) r48 (short) + c35 (short) rout2 rout2 + c37 (open) j8 mr-552ls 2 3 1 vss2 vss2 vss2 r46 (open) r44 (short) rout1 + c31 (short) rout1 + c33 (open) j6 mr-552ls 2 3 1 vss2 vss2 vss2 r49 (open) r47 (short) lout2 + c34 (short) lout2 + c36 (open) j7 mr-552ls 2 3 1 figure 4. analog output circuit for analog output, rca connector: j5 (lout1), j6 (rout1), j7 (lout2), j8 (rout2) are available to use. analog outputs are single-ended and output range of each channel is 2vrms(typ) when avdd1=avdd2=3.3vrms. < km103800> 2010/08 - 9 -
[AKD4686-B] ? digital input circuit (external dir: port1 rx0, port2 rx0) dgnd dgnd j12 mr-552ls 2 3 1 port1 rx0 c38 0.1u r55 75 port2 rx0 j15 mr-552ls 2 3 1 c49 0.1u r62 75 dgnd dgnd figure 5. digital input circuit (external dir) for digital input, rca connector: j12 (port1 rx0), j15 (port2 rx0) are available. ? digital output circuit (external dit: port1 tx1) r59 240 port1 tx1 dgnd dgnd j13 mr-552ls 2 3 1 r60 150 t1 da02f 1 5 4 8 figure 6. digital output circuit (external dit) for digital output, rca connector: j13 (port1 tx1) is available. < km103800> 2010/08 - 10 -
[AKD4686-B] control soft manual evaluation board and control soft settings 1. set an evaluation board properly. 2. connect the evaluation board to an ibm pc/at compatible pc by a 10wire flat cable. be aware of the direction of the 10pin header. when running this control soft on the windows 2000/xp, the driver which is included in the cd must be installed. refer to the ?dri ver control install manual for akm devi ce control software? for installing the driver. when running this control soft on the windows 95/98/me, driver installing is not necessary. this control soft does not support the windows nt. 3. proceed evaluation by follo wing the process below. operation screen 1. start up the control program following the process above. the operation screen is shown below. < km103800> 2010/08 - 11 -
[AKD4686-B] operation overview function, register map and testing tool can be controlled by th is control soft. these controls are selected by upper tabs. buttons which are frequently used such as register initializing button ?write default?, are located outside of the switching tab window. refer to the ? dialog boxes? for details of each dialog box setting. 1. [port reset]: for when connecting to usb i/f board (akdusbif-a) click this button after the control soft starts up when connecting usb i/f board (akdusbif-a). 2. [write default]: register initializing when the device is reset by a hardware reset, use this button to initialize the registers. 3. [all write]: executing write commands for all registers displayed. 4. [all read]: executing read comma nds for all registers displayed. 5. [save]: saving current register settings to a file. 6. [load]: executing data write from a saved file. 7. [all req write]: ?all req write? dialog box is popped up. 8. [data r/w]: ?data r/w? dialog box is popped up. 9. [sequence]: ?sequence? dialog box is popped up. 10. [sequence(file)]: ?sequence(file)? dialog box is popped up. 11. [read]: reading current register settings and display on to the register area (on the right of the main window). this is different from [all read] button, it does not reflect to a register map, only displaying hexadecimal. < km103800> 2010/08 - 12 -
[AKD4686-B] tab functions 1. [reg 0h ? 5h]: register map this tab is for a register writing and reading. each bit on the register map is a push-button switch. button down indicates ?h? or ?1? and the bit name is in red (when read only it is in deep red). button up indicates ?l? or ?0? and the bit name is in blue (when read only it is in gray) grayout registers are read only registers. they can not be controlled. the registers which is not defined in the datasheet are indicated as ?---?. < km103800> 2010/08 - 13 -
[AKD4686-B] [write]: data writing dialog it is for when changing two or more bits on the same address at the same time. click [write] button located on the right of th e each corresponded address for a pop-up dialog box. when checking the checkbox, the register will be ?h? or ?1?, when not checki ng the register will be ?l? or ?0?. click [ok] to write setting value to the registers, or click [cancel] to cancel this setting. [read]: data read click [read] button located on the right of the each corresponded address to execu te register reading. after register reading, the display will be updated regarding to th e register status. button down indicates ?h? or ?1? and the bit name is in red (when read only it is in deep red). button up indicates ?l? or ?0? and the bit name is in blue (when read only it is in gray) please be aware that button statuses will be changed by read command. < km103800> 2010/08 - 14 -
[AKD4686-B] 2. [tool]: testing tools this tab screen is for evaluation testing tool. click buttons for each testing tool. < km103800> 2010/08 - 15 -
[AKD4686-B] dialog boxes 1. [all req write]: all req write dialog box click [all reg write] button in the main window to open register setting files. register setting files saved by [save] button can be applied. [open (left)]: selecting a register setting file (*.akr). [write]: executing register writing. [write all]: executing all register writings. writings are executed in descending order. [help]: help window is popped up. [save]: saving the register setting file a ssignment. the file name is ?*.mar?. [open (right)]: opening a saved register setting file assignment ?*. mar?. [close]: closing the dialog box and finish the process. *operating suggestions (1) those files saved by [save] button and opened by [o pen] button on the right of the dialog ?*.mar? should be stored in the same folder. (2) when register settings are changed by [save] button in the main window, re-read the file to reflect new register settings. < km103800> 2010/08 - 16 -
[AKD4686-B] 2. [data r/w]: data r/w dialog box click the [data r/w] button in the main window for data read/write dialog box. data write is available to specified address. address box: input data address in hexadecimal numbers for data writing. data box: input data in hexadecimal numbers. mask box: input mask data in hexadecimal numbers. this is ?and? processed input data. [write]: writing to the address specified by ?address? box. [read]: reading from the address specified by ?address? box. the result will be shown in the read data box in hexadecimal numbers. [close]: closing the dialog box and finish the process. data writing can be cancelled by this button instead of [write] button. *the register map will be updated afte r executing [write] or [read] commands. < km103800> 2010/08 - 17 -
[AKD4686-B] 3. [sequence]: sequence dialog box click [sequence] button to open register sequence setting dialog box. register sequence can be set in this dialog box. sequence setting set register sequence by following process bellow. (1)select a command use [select] pull-down box to choose commands. corresponding boxes will be valid. < select pull-down menu > no_use: not using this address register: register writing reg(mask): register writing (masked) interval: taking an interval stop: pausing the sequence end: finishing the sequence (1) input sequence [address]: data address [data]: writing data [mask]: mask [data] box data is anded w ith [mask] box data. this is the actual writing data. when mask = 0x00, current setting is hold. when mask = 0xff, the 8bit data which is set in the [data] box is written. when mask =0x0f, lower 4bit da ta which is set in the [data] box is written. upper 4bit is hold to current setting. < km103800> 2010/08 - 18 -
[AKD4686-B] [ interval ]: interval time valid boxes for each process command are shown bellow. no_use: none register: [address], [data], [interval] reg(mask): [address], [data], [mask], [interval] interval: [interval] stop: none end: none < km103800> 2010/08 - 19 -
[AKD4686-B] control buttons the function of control button is shown bellow. [start]: executing the sequence [help]: opening a help window [save]: saving sequence settings as a file. the file name is ?*.aks?. [open]: opening a sequence setting file ?*.aks?. [close]: closing the dialog box and finish the process. stop of the sequence when ?stop? is selected in the sequence, processing is pa used and it starts again when [start] button is clicked. restarting step number is shown in the ?start step? box. when finishing the pr ocess until the end of sequence, ?start step? will return to ?1?. the sequence can be started from any step by writing the step number to the ?start step? box. write ?1? to the ?start step? box and click [start] button, when restarting the process from the beginning. < km103800> 2010/08 - 20 -
[AKD4686-B] 4. [sequence(file)]: sequence setting file dialog box click [sequence(file)] button to open sequence setting file dialog box. those files saved in the ?sequence setting dialog? can be applied in this dialog. [open (left)]: opening a sequence setting file (*.aks). [start]: executing the sequence setting. [start all]: executing all sequence settings. sequences are executed in descending order. [help]: pop up the help window. [save]: saving sequence setting file assi gnment. the file name is ?*.mas?. [open(right)]: opening a saved sequence setting file assignment ?*. mas?. [close]: closing the dialog box and finish the process. *operating suggestions (1) those files saved by [save] button and opened by [o pen] button on the right of the dialog ?*.mas? should be stored in the same folder. (2) when ?stop? is selected in the sequence the process will be paused and a pop-up message will appear. click ?ok? to continue the process. < km103800> 2010/08 - 21 -
[AKD4686-B] measure result 1) adc part [measurement condition] ? measurement unit : audio precision sys-2722 ? mclk : 512fs ? bick : 64fs ? fs : 48khz ? bw : 20hz 20khz (fs=48khz) ? bit : 24bit ? power supply : avdd1=avdd2=dvdd=cvdd=3.3v ? interface : external dit (u4) ? temperature : room temp results [db] parameter input signal measurement filter lch rch s/(n+d) 1khz, -1db 20klpf 88.1 87.7 dr 1khz, -60db 20klpf, a-weighted 97.5 97.4 s/n no signal 20klpf, a-weighted 97.5 97.5 < km103800> 2010/08 - 22 -
[AKD4686-B] 2) dac part [measurement condition] ? measurement unit : audio precision sys-2722 ? mclk : 512fs (fs=48khz), 256fs (fs=96khz), 128fs (fs=192khz) ? bick : 64fs ? fs : 48khz, 96khz, 192khz ? bw : 20hz 20khz (fs=48khz), 20hz 40khz (fs=96khz), 20hz 40khz (fs=192khz) ? resolution : 24bit ? power supply : avdd1=avdd2=dvdd=cvdd=3.3v ? interface : external dir (u4) ? temperature : room temp fs=48khz results [db] parameter input signal measurement filter lch rch s/(n+d) 1khz, 0db 20khz spcl 88.4 88.9 dr 1khz, -60db 20khz spcl 97.2 97.5 dr 1khz, -60db 20khz spcl, a-weighted 100.0 99.9 s/n ?0? data 20khz spcl 98.7 98.7 s/n ?0? data 20khz spcl, a-weighted 101.0 101.0 fs=96khz results [db] parameter input signal measurement filter lch rch s/(n+d) 1khz, 0db 40khz spcl 87.8 88.1 dr 1khz, -60db 40khz spcl 95.0 95.1 dr 1khz, -60db 40khz spcl, a-weighted 100.0 100.0 s/n ?0? data 40khz spcl 96.9 97.0 s/n ?0? data 40khz spcl, a-weighted 101.7 101.7 fs=192khz results [db] parameter input signal measurement filter lch rch s/(n+d) 1khz, 0db 40khz spcl 87.4 87.7 dr 1khz, -60db 40khz spcl 95.1 95.2 dr 1khz, -60db 40khz spcl, a-weighted 100.0 100.0 s/n ?0? data 40khz spcl 96.0 96.1 s/n ?0? data 40khz spcl, a-weighted 100.8 100.9 < km103800> 2010/08 - 23 -
[AKD4686-B] 1.adc ? (fs=48khz) -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 7. fft (input frequency =1khz, input level=-1dbfs) 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 8. fft(input frequency =1khz, input level=-60dbfs) < km103800> 2010/08 - 24 -
[AKD4686-B] 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s figure 9. fft(noise floor) -140 +0 -120 -100 -80 -60 -40 -20 dbr -120 -60 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 d b f s figure 10. thd + n vs input level (input frequency =1khz) < km103800> 2010/08 - 25 -
[AKD4686-B] 20 20k 50 100 200 500 1k 2k 5k 10k hz -120 -60 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 d b f s figure 11. thd + n vs input frequency (input level=-1.0dbfs) -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbr -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 5 55 5 figure 12. linearity (input frequency =1khz) < km103800> 2010/08 - 26 -
[AKD4686-B] 20 20k 50 100 200 500 1k 2k 5k 10k hz -2 +0 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 d b f s figure 13. frequency response (input level=-1.0dbfs) 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 -60 -130 -120 -110 -100 -90 -80 -70 d b 5555 555 figure 14. crosstalk (input level=-1.0dbfs) < km103800> 2010/08 - 27 -
[AKD4686-B] 2.dac ? (dac fs=48khz) 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 15. fft(input frequency =1khz, input level=0dbfs) 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 16. fft(input frequency =1khz, input level=-60dbfs) < km103800> 2010/08 - 28 -
[AKD4686-B] (dac fs=48khz) 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 17. fft(noise floor) 20 100k 50 100 200 500 1k 2k 5k 10k 20k 50k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 18. fft(out-of-band noise) < km103800> 2010/08 - 29 -
[AKD4686-B] (dac fs=48khz) -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -120 -60 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 d b r a figure 19. thd+n vs input le vel (input frequency =1khz) 20 20k 50 100 200 500 1k 2k 5k 10k hz -120 -60 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 d b r a figure 20. thd+n vs input frequency (input level=0dbfs) < km103800> 2010/08 - 30 -
[AKD4686-B] (dac fs=48khz) -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 21. linearity (input frequency =1khz) 20 20k 50 100 200 500 1k 2k 5k 10k hz -1 +1 -0.8 -0.6 -0.4 -0.2 +0 +0.2 +0.4 +0.6 +0.8 d b r a figure 22. frequency response (input level=0dbfs) < km103800> 2010/08 - 31 -
[AKD4686-B] (dac fs=48khz) 20 20k 50 100 200 500 1k 2k 5k 10k hz -140 -60 -130 -120 -110 -100 -90 -80 -70 d b figure 23. cross-talk (input level=0dbfs) < km103800> 2010/08 - 32 -
[AKD4686-B] (dac fs=96khz) 20 40k 50 100 200 500 1k 2k 5k 10k 20k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 24. fft(input frequency =1khz, input level=0dbfs) 20 40k 50 100 200 500 1k 2k 5k 10k 20k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 25. fft(input frequency =1khz, input level=-60dbfs) < km103800> 2010/08 - 33 -
[AKD4686-B] (dac fs=96khz) 20 40k 50 100 200 500 1k 2k 5k 10k 20k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 26. fft(noise floor) 20 100k 50 100 200 500 1k 2k 5k 10k 20k 50k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 27. fft (out of band noise) < km103800> 2010/08 - 34 -
[AKD4686-B] (dac fs=96khz) -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -120 -60 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 d b r a 5 5 figure 28. thd+n vs input le vel (input frequency =1khz) 20 40k 50 100 200 500 1k 2k 5k 10k 20k hz -120 -60 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 d b r a figure 29. thd+n vs fin (input level=0dbfs) < km103800> 2010/08 - 35 -
[AKD4686-B] (dac fs=96khz) -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 30. linearity (input frequency =1khz) 20 40k 50 100 200 500 1k 2k 5k 10k 20k hz -1 +1 -0.8 -0.6 -0.4 -0.2 +0 +0.2 +0.4 +0.6 +0.8 d b r a figure 31. frequency response (input level=0dbfs) < km103800> 2010/08 - 36 -
[AKD4686-B] (dac fs=96khz) 20 40k 50 100 200 500 1k 2k 5k 10k 20k hz -140 -60 -130 -120 -110 -100 -90 -80 -70 d b figure 32. cross-talk (input level=0dbfs) < km103800> 2010/08 - 37 -
[AKD4686-B] (dac fs=192khz) 20 80k 50 100 200 500 1k 2k 5k 10k 20k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 33. fft(input frequency =1khz, input level=0dbfs) 20 80k 50 100 200 500 1k 2k 5k 10k 20k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 34. fft(input frequency =1khz, input level=-60dbfs) < km103800> 2010/08 - 38 -
[AKD4686-B] (dac fs=192khz) 20 80k 50 100 200 500 1k 2k 5k 10k 20k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 35. fft(noise floor) 20 100k 50 100 200 500 1k 2k 5k 10k 20k 50k hz -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 36. fft (out of band noise) < km103800> 2010/08 - 39 -
[AKD4686-B] (dac fs=192khz) -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -120 -60 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 d b r a 5 figure 37. thd+n vs input le vel (input frequency =1khz) 20 80k 50 100 200 500 1k 2k 5k 10k 20k hz -120 -60 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 d b r a figure 38. thd+n vs input frequency (input level=0dbfs) < km103800> 2010/08 - 40 -
[AKD4686-B] (dac fs=192khz) -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a figure 39. linearity (f input frequency =1khz) 20 80k 50 100 200 500 1k 2k 5k 10k 20k hz -1 +1 -0.8 -0.6 -0.4 -0.2 +0 +0.2 +0.4 +0.6 +0.8 d b r a figure 40. frequency response (input level=0dbfs) < km103800> 2010/08 - 41 -
[AKD4686-B] (dac fs=192khz) 20 80k 50 100 200 500 1k 2k 5k 10k 20k hz -140 -60 -130 -120 -110 -100 -90 -80 -70 d b figure 41. cross-talk (input level=0dbfs) < km103800> 2010/08 - 42 -
[AKD4686-B] revision history date manual revision board revision reason page contents (yy/mm/dd) 2010/08/13 km103800 0 first edition important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the applica tion or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. < km103800> 2010/08 - 43 -
5 5 4 4 3 3 2 2 1 1 d d c c b b a a lin3 rin3 cvdd pdn bick2 mclk2 lrck2 sdti2 lout2 rout2 rout1 lout1 avdd1 avdd2 rin6 lin6 lin5 rin5 mt2n ms1 sdti1 mclk1 mt1n dvdd sdto bick1 lrck1 scl sda lin1 rin1 lin2 rin2 rin4 lin4 title size document number rev date: sheet of ak4686 0 AKD4686-B-main a3 16 friday, august 13, 2010 title size document number rev date: sheet of ak4686 0 AKD4686-B-main a3 16 friday, august 13, 2010 title size document number rev date: sheet of ak4686 0 AKD4686-B-main a3 16 friday, august 13, 2010 vss3 vss3 vss1 vss1 vss4 vss4 vss1 vss1 vss1 vss1 vss2 tp17 lout2 tp17 lout2 1 c4 0.1u c4 0.1u tp21 vss3 tp21 vss3 1 r27 0 r27 0 tp14 vss1 tp14 vss1 1 tp15 lout1 tp15 lout1 1 tp2 ms1 tp2 ms1 1 r18 0 r18 0 r3 0 r3 0 tp8 sdto tp8 sdto 1 + c2 10u + c2 10u r91 0 r91 0 tp5 mt1n tp5 mt1n 1 tp11 sda tp11 sda 1 tp25 lrck2 tp25 lrck2 1 tp27 bick2 tp27 bick2 1 tp20 vss2 tp20 vss2 1 tp23 pdn tp23 pdn 1 r20 0 r20 0 c17 0.1u c17 0.1u c6 0.1u c6 0.1u tp18 rout2 tp18 rout2 1 r90 0 r90 0 r19 0 r19 0 r2 0 r2 0 tp7 vss4 tp7 vss4 1 tp9 lrck1 tp9 lrck1 1 tp16 rout1 tp16 rout1 1 r17 0 r17 0 tp3 sdti1 tp3 sdti1 1 + c5 10u + c5 10u u1 ak4686 u1 ak4686 lin5 1 rin5 2 nc 3 lin6 4 rin6 5 avdd1 6 vss1 7 lout1 8 rout1 9 lout2 10 rout2 11 avdd2 12 vss2 13 cvee 14 cn 15 vss3 16 cp 17 cvdd 18 pdn 19 sdti2 20 lrck2 21 mclk2 22 bick2 23 nc 24 mt2n 25 ms1 26 sdti1 27 mclk1 28 mt1n 29 dvdd 30 vss4 31 sdto 32 lrck1 33 bick1 34 sda 35 scl 36 lin1 37 rin1 38 nc 39 lin2 40 rin2 41 nc 42 lin3 43 rin3 44 nc 45 lin4 46 rin4 47 nc 48 r23 0 r23 0 tp12 scl tp12 scl 1 + c21 10u + c21 10u c13 0.1u c13 0.1u tp13 avdd1 tp13 avdd1 1 tp26 mclk2 tp26 mclk2 1 r25 0 r25 0 r92 0 r92 0 tp24 sdti2 tp24 sdti2 1 r1 0 r1 0 tp1 mt2n tp1 mt2n 1 tp6 dvdd tp6 dvdd 1 c9 2.2u c9 2.2u + c12 10u + c12 10u tp19 avdd2 tp19 avdd2 1 r21 0 r21 0 tp10 bick1 tp10 bick1 1 c16 2.2u c16 2.2u tp4 mclk1 tp4 mclk1 1 r26 0 r26 0 -44-
5 5 4 4 3 3 2 2 1 1 d d c c b b a a lin1 lin2 lin3 lin4 lin5 lin6 rin1 rin2 rin3 rin4 rin5 rin6 rout2 lout2 lout1 rout1 title size document number rev date: sheet of analog input/output 0 AKD4686-B a3 26 friday, august 13, 2010 title size document number rev date: sheet of analog input/output 0 AKD4686-B a3 26 friday, august 13, 2010 title size document number rev date: sheet of analog input/output 0 AKD4686-B a3 26 friday, august 13, 2010 rin6 vss1 lin6 vss1 rin1 vss1 lin1 vss1 lin2 vss1 rin2 vss1 lin3 vss1 rin3 vss1 rin5 vss1 lin5 vss1 rin4 vss1 lin4 vss1 vss2 vss2 vss2 rout2 vss2 vss2 vss2 lout2 vss2 vss2 vss2 lout1 vss2 vss2 vss2 rout1 j8 mr-552ls j8 mr-552ls 2 3 1 r48 (short) r48 (short) r43 (short) r43 (short) jl5 mr-552ls jl5 mr-552ls 2 3 1 + c8 (short) + c8 (short) jr2 mr-552ls jr2 mr-552ls 2 3 1 jl4 mr-552ls jl4 mr-552ls 2 3 1 j5 mr-552ls j5 mr-552ls 2 3 1 + c30 (short) + c30 (short) c33 (open) c33 (open) + c35 (short) + c35 (short) + c29 (short) + c29 (short) + c27 (short) + c27 (short) + c3 (short) + c3 (short) + c14 (short) + c14 (short) + c26 (short) + c26 (short) jl3 mr-552ls jl3 mr-552ls 2 3 1 jl2 mr-552ls jl2 mr-552ls 2 3 1 jl6 mr-552ls jl6 mr-552ls 2 3 1 r49 (open) r49 (open) + c10 (short) + c10 (short) jr5 mr-552ls jr5 mr-552ls 2 3 1 + c7 (short) + c7 (short) r46 (open) r46 (open) jr4 mr-552ls jr4 mr-552ls 2 3 1 c37 (open) c37 (open) + c1 (short) + c1 (short) r47 (short) r47 (short) j7 mr-552ls j7 mr-552ls 2 3 1 j6 mr-552ls j6 mr-552ls 2 3 1 r44 (short) r44 (short) + c15 (short) + c15 (short) + c28 (short) + c28 (short) c32 (open) c32 (open) jr6 mr-552ls jr6 mr-552ls 2 3 1 + c11 (short) + c11 (short) r50 (open) r50 (open) jr1 mr-552ls jr1 mr-552ls 2 3 1 c36 (open) c36 (open) r45 (open) r45 (open) + c34 (short) + c34 (short) jl1 mr-552ls jl1 mr-552ls 2 3 1 jr3 mr-552ls jr3 mr-552ls 2 3 1 + c31 (short) + c31 (short) -45-
5 5 4 4 3 3 2 2 1 1 d d c c b b a a d3.3v d3.3v scl sda pdn d3.3v mt1n d3.3v mt2n d3.3v title size document number rev date: sheet of input/output 0 AKD4686-B a4 36 friday, august 13, 2010 title size document number rev date: sheet of input/output 0 AKD4686-B a4 36 friday, august 13, 2010 title size document number rev date: sheet of input/output 0 AKD4686-B a4 36 friday, august 13, 2010 up-i/f pdn hl scl sda sda(ack) dgnd dgnd dgnd dgnd mt1n hl dgnd mt2n hl dgnd r36 470 r36 470 r99 10k r99 10k r32 10k r32 10k d1 1s1588 d1 1s1588 a k c91 0.1u c91 0.1u r31 10k r31 10k port3 a1-10pa-2.54dsa port3 a1-10pa-2.54dsa 10 8 6 4 2 1 3 5 7 9 sw7 ate1d-2m3 sw7 ate1d-2m3 r38 (short) r38 (short) r41 10k r41 10k u2b 74ls07 u2b 74ls07 3 4 14 7 sw6 ate1d-2m3 sw6 ate1d-2m3 u8a 74hc14 u8a 74hc14 1 2 14 7 r40 10k r40 10k r37 100 r37 100 u3a 74hc14 u3a 74hc14 1 2 14 7 c25 0.1u c25 0.1u r35 10k r35 10k r33 470 r33 470 sw1 ate1d-2m3 sw1 ate1d-2m3 r34 100 r34 100 u2a 74ls07 u2a 74ls07 1 2 14 7 u8b 74hc14 u8b 74hc14 3 4 14 7 u8c 74hc14 u8c 74hc14 5 6 14 7 d5 1s1588 d5 1s1588 a k u8d 74hc14 u8d 74hc14 9 8 14 7 u3b 74hc14 u3b 74hc14 3 4 14 7 c83 0.1u c83 0.1u r39 10k r39 10k r42 100 r42 100 d4 1s1588 d4 1s1588 a k c92 0.1u c92 0.1u -46-
5 5 4 4 3 3 2 2 1 1 d d c c b b a a port1 cm0 port1 cm0 d3.3v d3.3v port1 ocks0 port1 ocks1 d3.3v d3.3v d3.3v d3.3v port1 ocks1 port1 ocks0 ex1 ex1 ms1 sdto bick1 lrck1 mclk1 sddir1 lrdir1 bidir1 mcdir1 sdti1 title size document number rev date: sheet of port 1 0 AKD4686-B a3 46 friday, august 13, 2010 title size document number rev date: sheet of port 1 0 AKD4686-B a3 46 friday, august 13, 2010 title size document number rev date: sheet of port 1 0 AKD4686-B a3 46 friday, august 13, 2010 dif1 ocks0 ocks1 port1 tx1 dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dif0 cm0 port1 dit/dir/4686 port1 pdn dgnd dgnd dgnd dgnd ex1 h l port1 rx0 ms1 dgnd lrck1 bick1 sdti1 gnd mclk1 mcko2 mcko1 gnd dif2 gnd gnd sdto c41 0.47u c41 0.47u c43 5p c43 5p jp20 mcko_sel1 jp20 mcko_sel1 r60 150 r60 150 d2 hsu119 d2 hsu119 k a j14 bnc j14 bnc 1 2 3 4 5 jp50 sdti1 jp50 sdti1 c42 0.1u c42 0.1u jp22 bick1_sel jp22 bick1_sel u5a 74hc04 u5a 74hc04 1 2 14 7 jp19 xti1 jp19 xti1 r58 1k r58 1k c38 0.1u c38 0.1u t1 da02f t1 da02f 1 5 4 8 c40 0.1u c40 0.1u j13 mr-552ls j13 mr-552ls 2 3 1 + c39 10u + c39 10u 1 2 + c47 10u + c47 10u 1 2 u3d 74hc14 u3d 74hc14 9 8 14 7 r57 10k r57 10k x1 24.576mhz x1 24.576mhz 1 2 r59 240 r59 240 sw2 ate1d-2m3 sw2 ate1d-2m3 jp21 mclk1_sel jp21 mclk1_sel c44 5p c44 5p u3c 74hc14 u3c 74hc14 5 6 14 7 r55 75 r55 75 jp24 sdto1_sel jp24 sdto1_sel jp25 ex150 jp25 ex150 j12 mr-552ls j12 mr-552ls 2 3 1 rp1 47k rp1 47k 1 2 3 4 5 6 7 8 9 r61 51 r61 51 + c48 10u + c48 10u 1 2 c46 0.1u c46 0.1u u6a 74vhc04 u6a 74vhc04 1 2 14 7 led1 erf led1 erf k a port1 a1-10pa-2.54dsa port1 a1-10pa-2.54dsa 1 3 5 7 9 10 8 6 4 2 jp23 lrck1_sel jp23 lrck1_sel sw3 sw3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c62 0.1u c62 0.1u r56 10k r56 10k u4 ak4118 u4 ak4118 ips0 1 nc 2 dif0 3 test2 4 dif1 5 nc 6 dif2 7 ips1 8 p/sn 9 xtl0 10 xtl1 11 tvdd 13 dvss 14 tx0 15 tx1 16 bout 17 cout 18 uout 19 vout 20 dvdd 21 dvss 22 mcko1 23 bick 26 mcko2 27 daux 28 xto 29 xti 30 pdn 31 cm0 32 cm1 33 ocks1 34 ocks0 35 int0 36 avdd 38 r 39 vcom 40 avss 41 rx0 42 nc 43 rx1 44 test1 45 rx2 46 nc 47 rx3 48 vin 12 lrck 24 sdto 25 int1 37 -47-
5 5 4 4 3 3 2 2 1 1 d d c c b b a a port2 cm0 port2 cm0 d3.3v d3.3v port2 ocks0 port2 ocks1 d3.3v d3.3v d3.3v d3.3v port2 ocks1 port2 ocks0 ex2 ex2 bick2 lrck2 mclk2 sdti2 mcdir1 bidir1 lrdir1 sddir1 title size document number rev date: sheet of port 2 0 AKD4686-B a3 56 friday, august 13, 2010 title size document number rev date: sheet of port 2 0 AKD4686-B a3 56 friday, august 13, 2010 title size document number rev date: sheet of port 2 0 AKD4686-B a3 56 friday, august 13, 2010 dgnd dgnd port2 dir port2 pdn h port2_rx0 dgnd d3.3v dif1 ocks0 ocks1 dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd ex2 dgnd dif0 dif2 cm0 dgnd lrck2 bick2 sdti2 gnd mclk2 dgnd sddir2 lrdir2 mcko2 mcko1 mcdir1 dgnd mcdir2 bidir2 gnd bidir1 lrdir1 sddir1 gnd gnd c51 0.1u c51 0.1u u3f 74hc14 u3f 74hc14 13 12 14 7 jp29 bick2_sel jp29 bick2_sel sw4 sw4 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 u3e 74hc14 u3e 74hc14 11 10 14 7 sw5 ate1d-2m3 sw5 ate1d-2m3 u7 ak4118 u7 ak4118 ips0 1 nc 2 dif0 3 test2 4 dif1 5 nc 6 dif2 7 ips1 8 p/sn 9 xtl0 10 xtl1 11 tvdd 13 dvss 14 tx0 15 tx1 16 bout 17 cout 18 uout 19 vout 20 dvdd 21 dvss 22 mcko1 23 bick 26 mcko2 27 daux 28 xto 29 xti 30 pdn 31 cm0 32 cm1 33 ocks1 34 ocks0 35 int0 36 avdd 38 r 39 vcom 40 avss 41 rx0 42 nc 43 rx1 44 test1 45 rx2 46 nc 47 rx3 48 vin 12 lrck 24 sdto 25 int1 37 port2 a1-10pa-2.54dsa port2 a1-10pa-2.54dsa 1 3 5 7 9 10 8 6 4 2 j15 mr-552ls j15 mr-552ls 2 3 1 c54 5p c54 5p c57 0.1u c57 0.1u + c59 10u + c59 10u 1 2 jp30 lrck2_sel jp30 lrck2_sel rp2 47k rp2 47k 1 2 3 4 5 6 7 8 9 r65 1k r65 1k jp27 mcko_sel2 jp27 mcko_sel2 j16 bnc j16 bnc 1 2 3 4 5 c49 0.1u c49 0.1u r63 10k r63 10k c56 0.1u c56 0.1u + c50 10u + c50 10u 1 2 jp32 ex250 jp32 ex250 + c58 10u + c58 10u 1 2 u5b 74hc04 u5b 74hc04 3 4 14 7 c53 0.1u c53 0.1u r64 10k r64 10k c52 0.47u c52 0.47u d3 hsu119 d3 hsu119 k a jp28 mclk2_sel jp28 mclk2_sel jp31 sdti2_sel jp31 sdti2_sel c55 5p c55 5p jp26 xti2 jp26 xti2 u6b 74vhc04 u6b 74vhc04 3 4 14 7 r66 51 r66 51 r62 75 r62 75 x2 24.576mhz x2 24.576mhz 1 2 led2 erf led2 erf k a -48-
5 5 4 4 3 3 2 2 1 1 d d c c b b a a tm_avdd1 tm_avdd2 tm_d3.3v tm_cvdd tm_avdd1 tm_avdd2 tm_d3.3v tm_cvdd tm_dvdd tm_+5v tm_dvdd tm_+5v tm_+5v avdd1 avdd2 d3.3v d3.3v cvdd dvdd d3.3v d3.3v d3.3v title size document number rev date: sheet of power supply 0 AKD4686-B a3 66 friday, august 13, 2010 title size document number rev date: sheet of power supply 0 AKD4686-B a3 66 friday, august 13, 2010 title size document number rev date: sheet of power supply 0 AKD4686-B a3 66 friday, august 13, 2010 dgnd vss4 avdd1 reg vss3 vss4 d3.3v avdd2 dgnd dgnd dgnd dgnd vss1 vss2 reg vss2 dgnd vss4 vss1 vss1 vss3 reg vss4 vss2 vss3 vss1 vss2 vss3 vss4 dvdd vss4 reg dgnd vss4 u8e 74hc14 u8e 74hc14 11 10 14 7 + c66 10u + c66 10u c81 0.1u c81 0.1u r78 (short) r78 (short) r77 (open) r77 (open) r76 (open) r76 (open) u6e 74vhc04 u6e 74vhc04 11 10 14 7 jp45 d3.3v_sel jp45 d3.3v_sel avdd1 t-45(o) avdd1 t-45(o) 1 vss4 t-45(b) vss4 t-45(b) 1 + c85 47u + c85 47u u2d 74ls07 u2d 74ls07 9 8 14 7 u8f 74hc14 u8f 74hc14 13 12 14 7 l7 (short) l7 (short) u6c 74vhc04 u6c 74vhc04 5 6 14 7 vss2 t-45(b) vss2 t-45(b) 1 u2e 74ls07 u2e 74ls07 11 10 14 7 l4 (short) l4 (short) u6d 74vhc04 u6d 74vhc04 9 8 14 7 c98 0.1u c98 0.1u r72 (short) r72 (short) c97 0.1u c97 0.1u l6 (short) l6 (short) c78 0.1u c78 0.1u l3 (short) l3 (short) c77 0.1u c77 0.1u t5 lm1117-3.3v t5 lm1117-3.3v in 3 gnd 1 out 2 + c73 47u + c73 47u l2 (short) l2 (short) vss1 t-45(b) vss1 t-45(b) 1 u5f 74hc04 u5f 74hc04 13 12 14 7 t2 lm1117-3.3v t2 lm1117-3.3v in 3 gnd 1 out 2 u5e 74hc04 u5e 74hc04 11 10 14 7 r74 (open) r74 (open) l5 (short) l5 (short) + c72 47u + c72 47u +5v1 t-45(o) +5v1 t-45(o) 1 jp42 dvdd_sel jp42 dvdd_sel u5c 74hc04 u5c 74hc04 5 6 14 7 c90 0.1u c90 0.1u + c79 47u + c79 47u d3.3v1 t-45(o) d3.3v1 t-45(o) 1 r73 (open) r73 (open) dgnd1 t-45(b) dgnd1 t-45(b) 1 u5d 74hc04 u5d 74hc04 9 8 14 7 r98 (short) r98 (short) + c76 10u + c76 10u dvdd1 t-45(o) dvdd1 t-45(o) 1 c80 0.1u c80 0.1u u2c 74ls07 u2c 74ls07 5 6 14 7 l1 (short) l1 (short) c82 0.1u c82 0.1u cvdd1 t-45(o) cvdd1 t-45(o) 1 jp40 avdd1_sel jp40 avdd1_sel r85 (open) r85 (open) + c99 10u + c99 10u u6f 74vhc04 u6f 74vhc04 13 12 14 7 r75 (open) r75 (open) + c71 47u + c71 47u jp41 avdd2_sel jp41 avdd2_sel + c96 10u + c96 10u avdd2 t-45(o) avdd2 t-45(o) 1 r79 (short) r79 (short) u2f 74ls07 u2f 74ls07 13 12 14 7 vss3 t-45(b) vss3 t-45(b) 1 -49-
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